Xilinx Spartan-3E 1600E Bedienungsanleitung PDF herunterladen (Seite 108)

106 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide

www.xilinx.com UG257 (v1.1) December 5, 2007

Chapter 13: DDR SDRAM

The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best

access to one of the FPGA’s Digital Clock Managers (DCMs). This path is required when

using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller

IP core documentation is also available from within the EDK 8.1i development software

(see “Related Resources,” page 109).

DDR SDRAM Connections

Table 13-1 shows the connections between the FPGA and the DDR SDRAM.

Table 1 3 -1: FPGA-to-DDR SDRAM Connections

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