Xilinx UG018 Bedienungsanleitung
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- Inhaltsverzeichnis
- LESEZEICHEN
- PowerPC™ 405 Processor 1
- Block Reference Guide 1
- 1-800-255-7778 2
- UG018 (v2.0) August 20, 2004 3
- Table of Contents 5
- Guide Contents 9
- Additional Resources 10
- Conventions 10
- Online Document 11
- Registers 12
- Register Descriptive Name 13
- Preface: About This Guide 14
- PowerPC Architecture 17
- Virtual Environment 19
- Operating Environment 19
- PowerPC 405 Software Features 21
- Privilege Modes 22
- Address Translation Modes 22
- Addressing Modes 23
- Data Types 23
- Register Set Summary 23
- General-Purpose Registers 24
- Special-Purpose Registers 25
- Machine-State Register 25
- Condition Register 25
- Device Control Registers 25
- Central-Processing Unit 26
- Exception Handling Logic 27
- Memory Management Unit 27
- Instruction and Data Caches 28
- Timer Resources 29
- PowerPC 405 Interfaces 29
- PowerPC 405 Performance 30
- Input/Output Interfaces 33
- Signal Naming Conventions 34
- UG018_02_01_051204 36
- C405CPMTIMERIRQ (Output) 39
- C405CPMTIMERRESETREQ (Output) 39
- C405CPMCORESLEEPREQ (Output) 39
- Virtex-4 Specific 40
- CPU Control Interface 41
- TIEC405MMUEN (Input) 42
- TIEC405DISOPERANDFWD (Input) 42
- Reset Interface 43
- UG018_03_102001 44
- C405RSTCORERESETREQ (Output) 45
- C405RSTCHIPRESETREQ (Output) 45
- C405RSTSYSRESETREQ (Output) 45
- RSTC405RESETCORE (Input) 46
- RSTC405RESETCHIP (Input) 46
- RSTC405RESETSYS (Input) 46
- JTGC405TRSTNEG (Input) 47
- Guarded Storage 50
- C405PLBICUREQUEST (Output) 52
- C405PLBICUABUS[0:29] (Output) 52
- C405PLBICUSIZE[2:3] (Output) 53
- C405PLBICUCACHEABLE (Output) 53
- C405PLBICUU0ATTR (Output) 54
- C405PLBICUABORT (Output) 54
- PLBC405ICUADDRACK (Input) 55
- PLBC405ICUSSIZE1 (Input) 55
- PLBC405ICURDDACK (Input) 56
- UG018_10_102001 57
- PLBC405ICUBUSY (Input) 58
- PLBC405ICUERR (Input) 59
- Abbreviation 61
- Description Where Used 61
- PLB/BIU Outputs: 62
- ISPLB Aborted Fetch Request 67
- Data-Side PLB Operation 68
- Address Pipelining 71
- Unaligned Accesses 71
- UG018_05_102001 72
- C405PLBDCUREQUEST (Output) 73
- C405PLBDCURNW (Output) 74
- C405PLBDCUABUS[0:31] (Output) 74
- C405PLBDCUSIZE2 (Output) 74
- C405PLBDCUCACHEABLE (Output) 75
- C405PLBDCUWRITETHRU (Output) 75
- C405PLBDCUU0ATTR (Output) 76
- C405PLBDCUGUARDED (Output) 76
- C405PLBDCUBE[0:7] (Output) 76
- Byte Enables [0:7] 77
- C405PLBDCUABORT (Output) 78
- PLBC405DCUADDRACK (Input) 80
- PLBC405DCUSSIZE1 (Input) 81
- PLBC405DCURDDACK (Input) 82
- PLBC405DCUWRDACK (Input) 83
- PLBC405DCUBUSY (Input) 84
- PLBC405DCUERR (Input) 84
- Table 2-20 100
- External DCR Bus Interface 101
- UG018_52_042304 102
- UG018_53_051204 103
- DCR Slave 103
- Processor Core 103
- Virtex-4-FX 104
- DCRC405ACK/EXTDCRACK (Input) 106
- PPC405 Outputs: 107
- DCR Outputs: 107
- UG018_07_102001 110
- EICC405CRITINPUTIRQ 110
- EICC405EXTINPUTIRQ 110
- PPC405 JTAG Debug Port 111
- JTAG Instruction Register 113
- UG018_70_100803 114
- UG018_71_100803 114
- UG018_76_032504 115
- UG018_75_032504 116
- PPC405 Cores) 117
- UG018_73_032504 118
- JTAG Logic 119
- Primitive 120
- Debug Interface 128
- DBGC405EXTBUSHOLDACK (Input) 129
- DBGC405DEBUGHALT (Input) 129
- C405DBGWBFULL (Output) 130
- C405DBGWBIAR[0:29] (Output) 130
- C405DBGWBCOMPLETE (Output) 130
- C405DBGMSRWE (Output) 130
- Trace Interface 131
- C405TRCCYCLE (Output) 133
- TRCC405TRIGGEREVENTIN (Input) 134
- TRCC405TRACEDISABLE (Input) 134
- If Unused Function 135
- MCBCPUCLKEN (Input) 136
- MCBJTAGEN (Input) 136
- MCBTIMEREN (Input) 137
- MCPPCRST (Input) 137
- Introduction 139
- Functional Features 140
- OCM Controller Operation 142
- Execution Re-ordering 144
- Store-data Bypass 144
- UG018_37b_12080 145
- UG018_37_020102 145
- DSOCM Input Ports 146
- DSOCM Input Ports: Attributes 147
- DSOCM Output Ports 148
- DSOCM-to-BRAM Interfaces 149
- *ENA can be tied off 150
- To/from FPGA logic 151
- (application-specific use 151
- Global signals from FPGA 151
- UG018_37c_042304 152
- UG018_38_020102 152
- UG018_38b_11210 153
- ISOCM Input Ports, Attributes 154
- ISOCM Output Ports 155
- UG018_49_112103 157
- Programmer’s Model 158
- DSCNTL Registers 159
- ISCNTL Registers 160
- UG018_46_042304 162
- UG018_46b_042304 163
- UG018_47_04230 164
- UG018_47b_05120 165
- DCR Write Access 166
- DCR Read Access 167
- UG018_69_042304 168
- UG018_69b_05120 169
- Single-Cycle Mode 170
- Multi-Cycle Mode 170
- ISOCM Instruction Fetching 170
- UG018_60_03060 171
- Writing to ISBRAM 172
- UG018_66_03060 173
- UG018_67_030603 174
- UG018_62_03060 175
- DSOCM Store, Fixed Latency 176
- Controller Only) 177
- UG018_62c_11210 178
- UG018_63c_112103 179
- UG018_64c_12080 180
- UG018_65c_12080 180
- References 181
- FCM Instruction Processing 184
- UG018_04_01_040904 184
- Resynchronization_Interface 184
- Instruction Classes 185
- Enabling the APU Controller 185
- Instruction Format 186
- Instruction Decoding 187
- FCM Load/Store Instructions 188
- Integer Divide Instructions 189
- FCM Exceptions 190
- FCM Instruction Flushing 190
- Execution Hazards 190
- APU Controller Configuration 191
- UDI Configuration Registers 192
- Interface Definition 193
- APU Controller Input Signals 194
- APU Controller Output Signals 196
- APU Controller Attributes 197
- APU Controller 198
- Configuration Field 198
- TIEAPUCONTROL Bits 198
- Autonomous Transactions 199
- UG018_04_03_032504 200
- Blocking Transactions 201
- Non-Blocking Transactions 202
- FCM Load Instruction 203
- FCM Store Instruction 204
- FCM Exception 205
- UG018_04_11_032504 206
- UG018_04_12_042304 206
- Appendix A 207
- RISCTrace Interface 209
- Signal Summary 213
- Appendix B: Signal Summary 214
- Processor Block Timing Model 223
- Parameter Function Signals 225
- UG012_C1_02_121701 232
Inhaltsverzeichnis
RPowerPC™ 405 Processor Block Reference GuideEmbedded Development KitUG018 (v2.0) August 20, 2004
10 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Preface: About This GuideRAdditional Resource
100 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRIn Virtex
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 101UG018 (v2.0) August 20, 2004 1-800-255-7778Rblocks that are associated with each PowerP
102 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRIn Virtex
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 103UG018 (v2.0) August 20, 2004 1-800-255-7778R(CPMC405CLOCK), the access times out. No er
104 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRVirtex-4-
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 105UG018 (v2.0) August 20, 2004 1-800-255-7778RExternal DCR Bus Interface I/O Signal Descr
106 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRThe proce
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 107UG018 (v2.0) August 20, 2004 1-800-255-7778RDCR Interface 1:1 Clocking, Latched Acknowl
108 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRDCR Inter
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 109UG018 (v2.0) August 20, 2004 1-800-255-7778RDCR Interface 1:2 Clocking, Latched Acknowl
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 11UG018 (v2.0) August 20, 2004 1-800-255-7778ROnline DocumentThe following conventions ar
110 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRinterrupt
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 111UG018 (v2.0) August 20, 2004 1-800-255-7778REIC Interface I/O Signal DescriptionsThe fo
112 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRJTAG Inte
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 113UG018 (v2.0) August 20, 2004 1-800-255-7778RC405JTGSHIFTDR (Output)This output is asser
114 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRThe six l
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 115UG018 (v2.0) August 20, 2004 1-800-255-7778RThe PPC405 cores do not have their own BSDL
116 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRFigure 2-
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 117UG018 (v2.0) August 20, 2004 1-800-255-7778RFigure 2-43: Correct Wiring of JTAG Chains
118 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRFigure 2-
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 119UG018 (v2.0) August 20, 2004 1-800-255-7778RConnecting PPC405 JTAG Logic in Series with
12 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Preface: About This GuideRGeneral Conventions
120 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRWhen the
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 121UG018 (v2.0) August 20, 2004 1-800-255-7778RFor devices with more than one PPC405 core,
122 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesR);end com
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 123UG018 (v2.0) August 20, 2004 1-800-255-7778R.C405JTGSHIFTDR (),.C405JTGUPDATEDR (),.C40
124 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRsignal TD
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 125UG018 (v2.0) August 20, 2004 1-800-255-7778R.C405JTGTDO (TDO_PPC),.JTGC405BNDSCANTDO ()
126 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRcomponent
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 127UG018 (v2.0) August 20, 2004 1-800-255-7778RU_JTAG : JTAGPPCport map (TDOTSPPC => TD
128 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesR.JTGC405B
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 129UG018 (v2.0) August 20, 2004 1-800-255-7778R Debug Interface I/O Signal DescriptionsThe
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 13UG018 (v2.0) August 20, 2004 1-800-255-7778RTermsTCR Timer-control registerTSR Timer-sta
130 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRIn system
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 131UG018 (v2.0) August 20, 2004 1-800-255-7778RC405DBGSTOPACK (Output)When asserted, this
132 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesR Trace In
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 133UG018 (v2.0) August 20, 2004 1-800-255-7778RFPGA logic can combine these signals with t
134 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRC405TRCTR
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 135UG018 (v2.0) August 20, 2004 1-800-255-7778RPVR Interface I/O Signal DescriptionsThe fo
136 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRAdditiona
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 137UG018 (v2.0) August 20, 2004 1-800-255-7778RMCBTIMEREN (Input)When asserted, this signa
138 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesR
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 139UG018 (v2.0) August 20, 2004 1-800-255-7778RChapter 3PowerPC 405 OCM ControllerIntrodu
14 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Preface: About This GuideRexception An abnorm
140 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRCompa
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 141UG018 (v2.0) August 20, 2004 1-800-255-7778RFeatures for Instruction-Side OCM (ISOCM)T
142 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerROCM C
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 143UG018 (v2.0) August 20, 2004 1-800-255-7778Rup with the value on the input ports: DSAR
144 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRregis
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 145UG018 (v2.0) August 20, 2004 1-800-255-7778RDSOCM PortsFigure 3-2 and Figure 3-3 are t
146 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRDSOCM
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 147UG018 (v2.0) August 20, 2004 1-800-255-7778RDSOCM Input Ports: AttributesAttributes ar
148 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRDSOCM
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 149UG018 (v2.0) August 20, 2004 1-800-255-7778RDSOCM-to-BRAM InterfacesFigure 3-4 provide
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 15UG018 (v2.0) August 20, 2004 1-800-255-7778ROEA The PowerPC operating-environment archit
150 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRFigur
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 151UG018 (v2.0) August 20, 2004 1-800-255-7778RNote: For backward compatibility with Virt
152 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRFigur
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 153UG018 (v2.0) August 20, 2004 1-800-255-7778RISOCM Input PortsTable 3-6 describes the I
154 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRISOCM
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 155UG018 (v2.0) August 20, 2004 1-800-255-7778RISOCM Output PortsTable 3-8 describes the
156 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRISOCM
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 157UG018 (v2.0) August 20, 2004 1-800-255-7778RFigure 3-9 shows an example of an ISOCM-to
158 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRNote:
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 159UG018 (v2.0) August 20, 2004 1-800-255-7778Rlocations. These bits are decoded against
16 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Preface: About This GuideRUISA The PowerPC us
160 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRISCNT
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 161UG018 (v2.0) August 20, 2004 1-800-255-7778RFeatures Introduced in Virtex-4 and Compar
162 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRFigur
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 163UG018 (v2.0) August 20, 2004 1-800-255-7778RFigure 3-12: DSOCM DCR Registers for Virte
164 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRFigur
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 165UG018 (v2.0) August 20, 2004 1-800-255-7778RThe following section describes the DCR bi
166 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRDCR W
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 167UG018 (v2.0) August 20, 2004 1-800-255-7778RDCR Read AccessIf the ISINIT register is r
168 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRFigur
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 169UG018 (v2.0) August 20, 2004 1-800-255-7778RBRAMs that interface with the ISOCM contro
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 17UG018 (v2.0) August 20, 2004 1-800-255-7778RChapter 1Introduction to the PowerPC 405 Pro
170 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRrouti
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 171UG018 (v2.0) August 20, 2004 1-800-255-7778RIn multi-cycle mode, initial wait cycles a
172 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRIn or
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 173UG018 (v2.0) August 20, 2004 1-800-255-7778Rmode and multi-cycle Mode. The timing inte
174 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRDSOCM
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 175UG018 (v2.0) August 20, 2004 1-800-255-7778RIn multi-cycle mode, initial wait cycles a
176 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRIn th
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 177UG018 (v2.0) August 20, 2004 1-800-255-7778Rperiod should be used. Note that this is o
178 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRDSOCM
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 179UG018 (v2.0) August 20, 2004 1-800-255-7778RDSOCM Data Store, Variable LatencyFigure 3
18 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
180 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerRFigur
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 181UG018 (v2.0) August 20, 2004 1-800-255-7778RApplication Notes and Reference DesignsXil
182 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 3: PowerPC 405 OCM ControllerR
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 183UG018 (v2.0) August 20, 2004 1-800-255-7778RChapter 4PowerPC 405 APU ControllerThis ch
184 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRThe A
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 185UG018 (v2.0) August 20, 2004 1-800-255-7778Rhas a configurable format and is a true ex
186 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRBlock
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 187UG018 (v2.0) August 20, 2004 1-800-255-7778RInstruction DecodingFCM instructions can b
188 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRThe d
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 189UG018 (v2.0) August 20, 2004 1-800-255-7778RThe extended op-code for Load/Store operat
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 19UG018 (v2.0) August 20, 2004 1-800-255-7778Rx Special-purpose registers for controlling
190 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRFCM U
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 191UG018 (v2.0) August 20, 2004 1-800-255-7778RFCM internal data hazards such as read-aft
192 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRUDI C
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 193UG018 (v2.0) August 20, 2004 1-800-255-7778RThe reset value of the individual UDI regi
194 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRAPU C
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 195UG018 (v2.0) August 20, 2004 1-800-255-7778RFCMAPUDCDLDSTWD FCM decoded load/store in
196 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRAPU C
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 197UG018 (v2.0) August 20, 2004 1-800-255-7778RAPU Controller AttributesThe following inp
198 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRTable
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 199UG018 (v2.0) August 20, 2004 1-800-255-7778RFCM Interface Timing SpecificationAutonomo
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com UG018 (v2.0) August 20, 20041-800-255-7778"Xilinx" and the Xilinx logo shown abo
20 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
200 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRNote:
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 201UG018 (v2.0) August 20, 2004 1-800-255-7778RBlocking TransactionsNote: Actual timing r
202 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRNon-B
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 203UG018 (v2.0) August 20, 2004 1-800-255-7778RFCM Load InstructionNote: Load data can ar
204 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRNote:
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 205UG018 (v2.0) August 20, 2004 1-800-255-7778RFCM ExceptionNote: FCMAPUEXEPTION may be s
206 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 4: PowerPC 405 APU ControllerRFCM D
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 207UG018 (v2.0) August 20, 2004 1-800-255-7778RAppendix ARISCWatch and RISCTrace Interfac
208 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix A: RISCWatch and RISCTrace Interf
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 209UG018 (v2.0) August 20, 2004 1-800-255-7778RRISCTrace InterfaceThe RISCTrace tool comm
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 21UG018 (v2.0) August 20, 2004 1-800-255-7778RPowerPC 405 Software FeaturesThe PowerPC 405
210 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix A: RISCWatch and RISCTrace Interf
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 211UG018 (v2.0) August 20, 2004 1-800-255-7778RTable A-4: PowerPC 405 to RISCTrace Signal
212 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix A: RISCWatch and RISCTrace Interf
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 213UG018 (v2.0) August 20, 2004 1-800-255-7778RAppendix BSignal SummaryInterface SignalsT
214 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix B: Signal SummaryRAPUFCMXERCA V-4
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 215UG018 (v2.0) August 20, 2004 1-800-255-7778RC405JTGCAPTUREDR (OUTPUT) V-II Pro and V-4
216 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix B: Signal SummaryRC405PLBICUABUS[
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 217UG018 (v2.0) August 20, 2004 1-800-255-7778RCPMC405TIMERCLKEN V-II Pro and V-4I CPM 1
218 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix B: Signal SummaryREICC405EXTINPUT
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 219UG018 (v2.0) August 20, 2004 1-800-255-7778RFCMAPUDONE V-4 I FCM 0 Indicates the compl
22 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
220 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix B: Signal SummaryRISOCMDCRBRAMRDS
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 221UG018 (v2.0) August 20, 2004 1-800-255-7778RPLBC405DCUWRDACK (INPUT) V-II Pro and V-4I
222 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix B: Signal SummaryRTIEC405DETERMIN
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 223UG018 (v2.0) August 20, 2004 1-800-255-7778RAppendix CProcessor Block Timing ModelThis
224 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix C: Processor Block Timing ModelRP
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 225UG018 (v2.0) August 20, 2004 1-800-255-7778RTable C-2: Parameters Relative to the Core
226 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix C: Processor Block Timing ModelRC
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 227UG018 (v2.0) August 20, 2004 1-800-255-7778R Table C-3: Parameters Relative to the DCR
228 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix C: Processor Block Timing ModelR
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 229UG018 (v2.0) August 20, 2004 1-800-255-7778RTPCKDO_FCM Data Outputs APUFCMINSTRUCTION[
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 23UG018 (v2.0) August 20, 2004 1-800-255-7778RReal ModeIn real mode, programs address phys
230 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix C: Processor Block Timing ModelR
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 231UG018 (v2.0) August 20, 2004 1-800-255-7778R Clock to Out: TPCKCO_ISOCM Control output
232 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Appendix C: Processor Block Timing ModelRF
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 233UG018 (v2.0) August 20, 2004 1-800-255-7778Aabortdata-side PLB 78, 97instruction-side
234 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Rcacheable 49non-cacheable request size 4
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 235UG018 (v2.0) August 20, 2004 1-800-255-7778Rprocessor resetSee core reset.programmable
236 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004R
24 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 25UG018 (v2.0) August 20, 2004 1-800-255-7778RSpecial-Purpose RegistersThe processor conta
26 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 27UG018 (v2.0) August 20, 2004 1-800-255-7778Rread ports and two write ports. During the d
28 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 29UG018 (v2.0) August 20, 2004 1-800-255-7778RTimer ResourcesThe PowerPC 405 contains a 64
UG018 (v2.0) August 20, 2004 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778PowerPC™ 405 Processor Block Reference Guide UG0
30 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 31UG018 (v2.0) August 20, 2004 1-800-255-7778Rcaches and the time associated with performi
32 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 1: Introduction to the PowerPC 405 Pr
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 33UG018 (v2.0) August 20, 2004 1-800-255-7778RChapter 2Input/Output InterfacesThis chapter
34 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRAppendix B
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 35UG018 (v2.0) August 20, 2004 1-800-255-7778RClock and Power Management InterfaceThe cloc
36 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRi The DBGC
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 37UG018 (v2.0) August 20, 2004 1-800-255-7778RCPM Interface I/O Signal DescriptionsThe fol
38 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRCPMC405TIM
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 39UG018 (v2.0) August 20, 2004 1-800-255-7778RC405CPMMSREE, C405CPMMSRCE, and C405CPMTIMER
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com UG018 (v2.0) August 20, 20041-800-255-7778
40 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRx PLBCLK,
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 41UG018 (v2.0) August 20, 2004 1-800-255-7778Rclocks for the OCM controllers in the proces
42 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRCPU Contro
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 43UG018 (v2.0) August 20, 2004 1-800-255-7778Rinstructions following the load require the
44 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRJTGC405TRS
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 45UG018 (v2.0) August 20, 2004 1-800-255-7778RReset Interface I/O Signal DescriptionsThe f
46 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRRSTC405RES
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 47UG018 (v2.0) August 20, 2004 1-800-255-7778RTable 2-5, page 44 shows the valid combinati
48 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRx The requ
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 49UG018 (v2.0) August 20, 2004 1-800-255-7778Rplaced in the ICU fill buffer, but not in th
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 5UG018 (v2.0) August 20, 2004 1-800-255-7778Preface: About This GuideGuide Contents . . .
50 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRx The pref
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 51UG018 (v2.0) August 20, 2004 1-800-255-7778RInstruction-Side PLB Interface I/O Signal De
52 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRC405PLBICU
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 53UG018 (v2.0) August 20, 2004 1-800-255-7778RC405PLBICUSIZE[2:3] (Output)These signals ar
54 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRC405PLBICU
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 55UG018 (v2.0) August 20, 2004 1-800-255-7778RPLBC405ICUADDRACK (Input)When asserted, this
56 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRx When a 6
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 57UG018 (v2.0) August 20, 2004 1-800-255-7778RThe ICU reads either the low 32 bits or the
58 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRtransfer o
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 59UG018 (v2.0) August 20, 2004 1-800-255-7778RFollowing reset, the processor block prevent
6 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004RInstruction-Side PLB Operation. . . . . . . .
60 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRfastest ra
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 61UG018 (v2.0) August 20, 2004 1-800-255-7778RISPLB Non-Pipelined Cacheable Sequential Fet
62 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRISPLB Non-
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 63UG018 (v2.0) August 20, 2004 1-800-255-7778RThe first line read (rl1) is requested by th
64 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRAfter the
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 65UG018 (v2.0) August 20, 2004 1-800-255-7778Rin cycles 10 through 15). The line is not ca
66 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRISPLB 2:1
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 67UG018 (v2.0) August 20, 2004 1-800-255-7778RISPLB 3:1 Core-to-PLB Line FetchThe timing d
68 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRData-Side
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 69UG018 (v2.0) August 20, 2004 1-800-255-7778Rx The target address of the data to be acces
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 7UG018 (v2.0) August 20, 2004 1-800-255-7778RISOCM Controller Instruction Fetch Operation
70 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRi An eight
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 71UG018 (v2.0) August 20, 2004 1-800-255-7778RAn eight-word line-write transfer occurs whe
72 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesR Figure 2-
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 73UG018 (v2.0) August 20, 2004 1-800-255-7778RData-Side PLB Interface I/O Signal Descripti
74 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRIf the tra
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 75UG018 (v2.0) August 20, 2004 1-800-255-7778RAn eight-word line transfer moves the cache
76 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRC405PLBDCU
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 77UG018 (v2.0) August 20, 2004 1-800-255-7778RTable 2-13 shows the possible values that ca
78 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRC405PLBDCU
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 79UG018 (v2.0) August 20, 2004 1-800-255-7778Ran aborted data-write request. In this case,
8 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004RFCM Store Instruction . . . . . . . . . . . .
80 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRPLBC405DCU
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 81UG018 (v2.0) August 20, 2004 1-800-255-7778Rmust abort a DCU request (move no data) if t
82 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRx During a
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 83UG018 (v2.0) August 20, 2004 1-800-255-7778RPLBC405DCURDWDADDR[1:3] (Input)These signals
84 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRis transfe
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 85UG018 (v2.0) August 20, 2004 1-800-255-7778RThe PLB slave should latch error information
86 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRx The DCU
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 87UG018 (v2.0) August 20, 2004 1-800-255-7778RThe second line read (rl2) is requested by t
88 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRis sent fr
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 89UG018 (v2.0) August 20, 2004 1-800-255-7778RThe second word read (rw2) is requested by t
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 9UG018 (v2.0) August 20, 2004 1-800-255-7778RPrefaceAbout This GuideThis guide serves as a
90 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRThe third
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 91UG018 (v2.0) August 20, 2004 1-800-255-7778RDSPLB Three Consecutive Word WritesThe timin
92 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRDSPLB Line
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 93UG018 (v2.0) August 20, 2004 1-800-255-7778RDSPLB Word Write/Word Read/Word Write/Line R
94 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRDSPLB Word
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 95UG018 (v2.0) August 20, 2004 1-800-255-7778RDSPLB 2:1 Core-to-PLB Line ReadThe timing di
96 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRDSPLB 3:1
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 97UG018 (v2.0) August 20, 2004 1-800-255-7778RDSPLB Aborted Data-Access RequestThe timing
98 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide1-800-255-7778 UG018 (v2.0) August 20, 2004Chapter 2: Input/Output InterfacesRDevice-Con
PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 99UG018 (v2.0) August 20, 2004 1-800-255-7778RInternal Device Control Register (DCR) Inter
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