Xilinx LOGICORE UG144 Bedienungsanleitung PDF herunterladen (Seite 116)

116 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide

UG144 April 24, 2009

Chapter 11: Interfacing to Other Cores

-- DISCONTINUED PRODUCT --

Figure 11-2 illustrates the following:

• Direct internal connections are made between the GMII interfaces between the two

cores.

• If the GEMAC has been generated with the optional Management Interface, the

MDIO port can be connected up to that of the Ethernet 1000BASE-X PCS/PMA or

SGMII core to access its embedded configuration and status registers. See “Using the

Optional Management Interface.”

• Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE-X PCS/PMA

or SGMII core, the entire GMII is synchronous to a single clock domain. For this

reason, userclk2 is used as the 125 MHz reference clock for both cores and the

transmitter and receiver logic of the GEMAC core now operate in the same clock

domain. This allows clock crossing constraints between the gtx_clk and

gmii_rx_clk clock domains to be removed from the GEMAC UCF. See “Timespecs

for Critical Logic within the Core.”

1 2 ... 111 112 113 114 115 116 117 118 119 120 121 ... 137 138

Keine Kommentare

Xilinx LOGICORE UG144 Bedienungsanleitung Seite 116