Xilinx SP601 Hardware UG518 Bedienungsanleitung PDF herunterladen (Seite 38)

38 www.xilinx.com SP601 Hardware User Guide

UG518 (v1.1) August 19, 2009

Chapter 1: SP601 Evaluation Board

GPIO Male Pin Header

The SP601 provides a 2X6 GPIO male pin header supporting 3.3V power, GND and eight

I/Os. Figure 1-26 and Table 1-20 describe the J13 GPIO Male Pin Header.

X-Ref Target - Figure 1-26

Figure 1-26: GPIO Male Pin Header Topology

7 8

910

11 12

J13

VCC3V3

GPIO HDR4

GPIO HDR0

GPIO HDR1

GPIO HDR2

GPIO HDR3

GPIO HDR5

GPIO HDR6

GPIO HDR7

R100 R101

R102 R103

200 200

200

5% 5%

1/16W 1/16W

1/16W

R99

200

1/16W

R98

200

1/16W

R97

200

1/16W

R96

200

1/16W

UG518_24_070809

Table 1-20: GPIO Header Pins

FPGA U1 Pin Signal Name J13 Pin

N17 GPIO_HDR0 1

M18 GPIO_HDR1 3

A3 GPIO_HDR2 5

L15 GPIO_HDR3 7

F15 GPIO_HDR4 2

B4 GPIO_HDR5 4

F13 GPIO_HDR6 6

P12 GPIO_HDR7 8

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 54 55

SP601 Hardware 1
User Guide 1
Revision History 3
Table of Contents 5
Appendix A: References 6
Appendix D: SP601 Master UCF 6
About This Guide 7
Online Document 8
SP601 Evaluation Board 9
Features 10
Related Xilinx Documents 11
Detailed Description 12
Configuration 13
I/O Voltage Rails 13
References 14
X-Ref Target - Figure 1-3 16
3. SPI x4 Flash 18
4. Linear Flash BPI 20
UG518 (v1.1) August 19, 2009 23
6. USB-to-UART Bridge 25
7. IIC Bus 26
8. Clock Generation 27
SMA Connectors (Differential) 28
Table 1-13: LPC Pinout 29
10. Status LEDs 32
12. FPGA INIT and DONE LEDs 34
13. User I/O 35
User DIP switch 36
User Pushbutton Switches 37
GPIO Male Pin Header 38
Power Management 40
Configuration Options 42
Appendix A: References 46
Appendix B 47
VITA 57.1 FMC Connections 49
SP601 Master UCF 51
Appendix D: SP601 Master UCF 52

Kommentare zu diesen Handbüchern

Keine Kommentare

Xilinx SP601 Hardware UG518 Bedienungsanleitung Seite 38

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Hardware Xilinx SP601 Hardware UG518