Xilinx ML605 Bedienungsanleitung

ML605 Hardware User GuideUG534 (v1.8) October 2, 2012

10 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardFeaturesThe ML605 provides the following featu

ML605 Hardware User Guide www.xilinx.com 11UG534 (v1.8) October 2, 2012Overview• 16. Status LEDs•Ethernet status•FPGA INIT•FPGA DONE•System ACE CF Sta

12 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardBlock DiagramFigure 1-1 shows a high-level blo

ML605 Hardware User Guide www.xilinx.com 13UG534 (v1.8) October 2, 2012Detailed DescriptionDetailed DescriptionFigure 1-2 shows a board photo with num

14 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board7Clock generation200 MHz OSC, oscillator socke

ML605 Hardware User Guide www.xilinx.com 15UG534 (v1.8) October 2, 2012Detailed Description1. Virtex-6 XC6VLX240T-1FFG1156 FPGAA Virtex-6 XC6VLX240T-1

16 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardThe ML605 supports Master BPI-Up, JTAG, and Sl

ML605 Hardware User Guide www.xilinx.com 17UG534 (v1.8) October 2, 2012Detailed DescriptionReferencesSee the Xilinx Virtex-6 FPGA documentation for mo

18 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardA15 DDR3_A6 90 A6B15 DDR3_A7 86 A7G15 DDR3_A8

ML605 Hardware User Guide www.xilinx.com 19UG534 (v1.8) October 2, 2012Detailed DescriptionG12 DDR3_D20 40 DQ20G13 DDR3_D21 42 DQ21F14 DDR3_D22 50 DQ2

ML605 Hardware User Guide www.xilinx.com UG534 (v1.8) October 2, 2012© Copyright 2009–2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, S

20 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardE24 DDR3_D54 174 DQ54G25 DDR3_D55 176 DQ55F28

ML605 Hardware User Guide www.xilinx.com 21UG534 (v1.8) October 2, 2012Detailed DescriptionThe Memory Interface Generator (MIG) tool guidelines specif

22 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board3. 128 Mb Platform Flash XLA 128 Mb Xilinx XCF

ML605 Hardware User Guide www.xilinx.com 23UG534 (v1.8) October 2, 2012Detailed DescriptionML605 Flash Boot OptionsThe ML605 has two parallel wired fl

24 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardAF24 FLASH_D0 34 DQ0 F2 DQ00AF25 FLASH_D1 36 D

ML605 Hardware User Guide www.xilinx.com 25UG534 (v1.8) October 2, 2012Detailed DescriptionFPGA Design Considerations for the Configuration FlashAfter

26 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board5. System ACE CF and CompactFlash ConnectorThe

ML605 Hardware User Guide www.xilinx.com 27UG534 (v1.8) October 2, 2012Detailed DescriptionTable 1-6 lists the System ACE CF connections.ReferencesSee

28 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board6. USB JTAGJTAG configuration is provided thro

ML605 Hardware User Guide www.xilinx.com 29UG534 (v1.8) October 2, 2012Detailed DescriptionThe JTAG chain can be used to program the FPGA and access t

UG534 (v1.8) October 2, 2012 www.xilinx.com ML605 Hardware User Guide06/19/12 1.7 Added [Ref 4] link to Oscillator (Differential), page 29. Revised Os

30 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardX-Ref Target - Figure 1-7Figure 1-7: ML605 Osc

ML605 Hardware User Guide www.xilinx.com 31UG534 (v1.8) October 2, 2012Detailed DescriptionSMA Connectors (Differential)A high-precision clock signal

32 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardGTX SMA ClockThe ML605 includes a pair of SMA

ML605 Hardware User Guide www.xilinx.com 33UG534 (v1.8) October 2, 2012Detailed Description8. Multi-Gigabit Transceivers (GTX MGTs)The ML605 provides

34 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board9. PCI Express Endpoint ConnectivityThe 8-lane

ML605 Hardware User Guide www.xilinx.com 35UG534 (v1.8) October 2, 2012Detailed DescriptionTable 1-8 shows the PCIe connector (P1) that provides up to

36 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardThe PCIe interface obtains its power from the

ML605 Hardware User Guide www.xilinx.com 37UG534 (v1.8) October 2, 2012Detailed DescriptionReferencesSee the following websites for more Virtex-6 FPGA

38 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board11. 10/100/1000 Tri-Speed Ethernet PHYThe ML60

ML605 Hardware User Guide www.xilinx.com 39UG534 (v1.8) October 2, 2012Detailed DescriptionSGMII GTX Transceiver Clock GenerationAn Integrated Circuit

ML605 Hardware User Guide www.xilinx.com UG534 (v1.8) October 2, 2012

40 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardReferencesSee the Marvell Alaska Gigabit Ether

ML605 Hardware User Guide www.xilinx.com 41UG534 (v1.8) October 2, 2012Detailed Description12. USB-to-UART BridgeThe ML605 contains a Silicon Labs CP2

42 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board13. USB ControllerThe ML605 provides USB suppo

ML605 Hardware User Guide www.xilinx.com 43UG534 (v1.8) October 2, 2012Detailed Description14. DVI CodecThe ML605 features a DVI connector (P3) to sup

44 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board15. IIC BusThe ML605 implements four IIC bus i

ML605 Hardware User Guide www.xilinx.com 45UG534 (v1.8) October 2, 2012Detailed DescriptionX-Ref Target - Figure 1-14Figure 1-14: IIC Bus TopologyU1J6

46 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board8 Kb NV MemoryThe ML605 hosts an 8 Kb ST Micro

ML605 Hardware User Guide www.xilinx.com 47UG534 (v1.8) October 2, 2012Detailed Description16. Status LEDsTable 1-19 defines the status LEDs. Table 1-

48 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardEthernet PHY Status LEDsThe Ethernet PHY statu

ML605 Hardware User Guide www.xilinx.com 49UG534 (v1.8) October 2, 2012Detailed DescriptionFPGA INIT and DONE LEDsThe typical Xilinx FPGA power up and

ML605 Hardware User Guide www.xilinx.com 5UG534 (v1.8) October 2, 2012Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . .

50 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardUser LEDsThe ML605 provides two groups of acti

ML605 Hardware User Guide www.xilinx.com 51UG534 (v1.8) October 2, 2012Detailed DescriptionUser Pushbutton SwitchesThe ML605 provides six active-High

52 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardUser DIP SwitchThe ML605 includes an active-Hi

ML605 Hardware User Guide www.xilinx.com 53UG534 (v1.8) October 2, 2012Detailed DescriptionUser SMA GPIOThe ML605 includes an pair of SMA connectors f

54 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardLCD Display (16 Character x 2 Lines)The ML605

ML605 Hardware User Guide www.xilinx.com 55UG534 (v1.8) October 2, 2012Detailed Description18. Switches The ML605 Evaluation board includes the follow

56 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardFPGA_PROG_B Pushbutton SW4 (Active-Low)This sw

ML605 Hardware User Guide www.xilinx.com 57UG534 (v1.8) October 2, 2012Detailed DescriptionSystem ACE CF CompactFlash Image Select DIP Switch S1System

58 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardMode, Osc Enable, Boot EEPROM Select, and Addr

ML605 Hardware User Guide www.xilinx.com 59UG534 (v1.8) October 2, 2012Detailed DescriptionSee 3. 128 Mb Platform Flash XL, page 22 and 4. 32 MB Linea

6 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012FPGA_PROG_B Pushbutton SW4 (Active-Low). . . . . . . . . . . . . . . . . . . . .

60 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation Board•2 MGT clocks•4 differential clocksNote:The ML

ML605 Hardware User Guide www.xilinx.com 61UG534 (v1.8) October 2, 2012Detailed DescriptionC10 FMC_HPC_LA06_P AG20 D11 FMC_HPC_LA05_P AG22C11 FMC_HPC_

62 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardE25 FMC_HPC_HB05_N AN34 F25 FMC_HPC_HB04_P AM3

ML605 Hardware User Guide www.xilinx.com 63UG534 (v1.8) October 2, 2012Detailed DescriptionG37 FMC_HPC_LA33_N AH24 H37 FMC_HPC_LA32_P AG25H38 FMC_HPC_

64 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardTable 1-29: Power Supply Voltages for HPC Conn

ML605 Hardware User Guide www.xilinx.com 65UG534 (v1.8) October 2, 2012Detailed Description20. VITA 57.1 FMC LPC ConnectorThe ML605 implements both th

66 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardTable 1-30 shows the VITA 57.1 FMC LPC connect

ML605 Hardware User Guide www.xilinx.com 67UG534 (v1.8) October 2, 2012Detailed DescriptionReferencesSee the data sheet for the ROHS compliant FMC HPC

68 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardOnboard Power RegulationFigure 1-28 shows the

ML605 Hardware User Guide www.xilinx.com 69UG534 (v1.8) October 2, 2012Detailed DescriptionTable 1-31: Onboard Power System DevicesDevice TypeReferenc

ML605 Hardware User Guide www.xilinx.com 7UG534 (v1.8) October 2, 2012PrefaceAbout This GuideThis manual accompanies the Virtex®-6 FPGA ML605 Evaluati

70 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardVoltage and current monitoring and control are

ML605 Hardware User Guide www.xilinx.com 71UG534 (v1.8) October 2, 2012Detailed Description22. System MonitorThe System Monitor provides information r

72 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardSystem Monitor Header (J35)Figure 1-30 shows t

ML605 Hardware User Guide www.xilinx.com 73UG534 (v1.8) October 2, 2012Detailed DescriptionML605 Board Power MonitorIn addition to monitoring the FPGA

74 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardFan ControllerIn highly demanding situations,

ML605 Hardware User Guide www.xilinx.com 75UG534 (v1.8) October 2, 2012Detailed DescriptionFPGA Power Supply MarginingThe PMBus (IIC), which provides

76 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Chapter 1: ML605 Evaluation BoardConfiguration OptionsThe FPGA on the ML605 Eva

ML605 Hardware User Guide www.xilinx.com 77UG534 (v1.8) October 2, 2012Appendix AReferencesThis section provides references to documentation supportin

78 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix A: ReferencesAdditional documentation:22. Micron Technology, Inc., DDR

ML605 Hardware User Guide www.xilinx.com 79UG534 (v1.8) October 2, 2012Appendix BDefault Switch and Jumper SettingsTab l e B - 3 4: Default Switch Se

8 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Preface: About This Guide• Virtex-6 FPGA Memory Resources User GuideThe function

80 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix B: Default Switch and Jumper SettingsTab l e B - 3 5: Default Jumper

ML605 Hardware User Guide www.xilinx.com 81UG534 (v1.8) October 2, 2012Appendix CVITA 57.1 FMC LPC (J63) and HPC (J64) Connector PinoutFigure C-34 sho

82 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix C: VITA 57.1 FMC LPC (J63) and HPC (J64) Connector PinoutFigure C-35 s

ML605 Hardware User Guide www.xilinx.com 83UG534 (v1.8) October 2, 2012Appendix DML605 Master UCFThe UCF template is provided for designs that target

84 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix D: ML605 Master UCFNET "DDR3_D5" LOC =

ML605 Hardware User Guide www.xilinx.com 85UG534 (v1.8) October 2, 2012NET "DDR3_DM6" LOC = "A29"; ## 170

86 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix D: ML605 Master UCFNET "FLASH_A18" LOC =

ML605 Hardware User Guide www.xilinx.com 87UG534 (v1.8) October 2, 2012NET "FMC_HPC_DP5_M2C_P" LOC = "AL3"; ## A18

88 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix D: ML605 Master UCFNET "FMC_HPC_HB02_N" LOC =

ML605 Hardware User Guide www.xilinx.com 89UG534 (v1.8) October 2, 2012NET "FMC_HPC_LA14_P" LOC = "AN19"; ## C18

ML605 Hardware User Guide www.xilinx.com 9UG534 (v1.8) October 2, 2012Chapter 1ML605 Evaluation BoardOverviewThe ML605 board enables hardware and soft

90 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix D: ML605 Master UCFNET "FMC_LPC_LA05_P" LOC =

ML605 Hardware User Guide www.xilinx.com 91UG534 (v1.8) October 2, 2012## NET "FPGA_FWE_B" LOC = "AF23"; ## SEE

92 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix D: ML605 Master UCFNET "PCIE_RX0_P" LOC =

ML605 Hardware User Guide www.xilinx.com 93UG534 (v1.8) October 2, 2012NET "PMBUS_ALERT_LS" LOC = "AH9"; ## 2

94 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix D: ML605 Master UCFNET "USB_D3_LS" LOC =

ML605 Hardware User Guide www.xilinx.com 95UG534 (v1.8) October 2, 2012Appendix ERegulatory and Compliance InformationThis product is designed and tes

96 www.xilinx.com ML605 Hardware User GuideUG534 (v1.8) October 2, 2012Appendix E: Regulatory and Compliance InformationMarkingsThis product complies