Xilinx SP605 Bedienungsanleitung PDF herunterladen (Seite 53)

SP605 Hardware User Guide www.xilinx.com 53

UG526 (v1.8) September 24, 2012

Detailed Description

18. VITA 57.1 FMC LPC Connector

The SP605 implements the Low Pin Count (LPC, J2) connector option of the VITA 57.1.1

FMC specification.

Note:

The FMC LPC J2 connector is a keyed connector oriented so that a plug-on card faces away

from the SP605 board.

The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low

Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector

form factor is used for both versions. The HPC version is fully populated with 400 pins

present, and the LPC version is partially populated with 160 pins.

The 10 x 40 rows of a FMC LPC connector provides connectivity for:

• 68 single-ended or 34 differential user defined signals

•1 MGT

•1 MGT clock

•2 differential clocks

• 61 ground, 10 power connections

Of the above signal and clock connectivity capability, the SP605 implements the full set:

• 34 differential user-defined pairs

• 34 LA pairs

•1 MGT

•1 MGT clock

•2 differential clocks

Note:

The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V (non-

adjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are compatible

with 2.5V mezzanine cards capable of supporting 2.5V VADJ.

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 73 74

Keine Kommentare

Xilinx SP605 Bedienungsanleitung Seite 53