Xilinx ChipScope PLB46 IBA v1.00a Bedienungsanleitung

DS619 April 7, 2009 www.xilinx.com 1Product Specification© 2009 Xilinx, Inc. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other desi

10 www.xilinx.com DS619 April 7, 2009Product SpecificationTable 2 lists the IBA PLBv46 parameterized features, which control the ports attached to the

DS619 April 7, 2009 www.xilinx.com 11Product SpecificationEvery match unit group has a match type and match counter width parameter. The match unit t

12 www.xilinx.com DS619 April 7, 2009Product SpecificationDesign ImplementationThe ChipScope PLB IBA design is implemented in a Tcl script. When the E

DS619 April 7, 2009 www.xilinx.com 13Product SpecificationRevision HistoryNotice of DisclaimerXilinx is providing this design, code, or information (c

2 www.xilinx.com DS619 April 7, 2009Product SpecificationChipScope PLB46 IBA I/O SignalsTable 1: IBA_PLBv46 Pin Descriptions Port MU Signal Name Inte

DS619 April 7, 2009 www.xilinx.com 3Product SpecificationP32 MU_2B PLB_masterID[0: C_PLBV46_MID_WIDTH-1]Slave I PLB current master identifierP33 MU_2B

4 www.xilinx.com DS619 April 7, 2009Product SpecificationP54 MU_9 Sl_MWrErr[0: C_PLBV46_NUM_SLAVES *C_PLBV46_NUM_MASTERS-1]Slave I Slave write error i

DS619 April 7, 2009 www.xilinx.com 5Product SpecificationThe IBA_PLBv46 ports listed in Table 1 connect to the PLBv46 bus. The core divides related po

6 www.xilinx.com DS619 April 7, 2009Product SpecificationWhen these match units are enabled, all slaves or masters are enabled. You cannot individuall

DS619 April 7, 2009 www.xilinx.com 7Product SpecificationG13 Enable Trigger Out C_ENABLE_TRIGGER_OUT 1,0 0 IntegerTrigger In, PLB Reset, and PLB Error

8 www.xilinx.com DS619 April 7, 2009Product SpecificationG32 1=Enable storing MU 3 signals in the data sample storage buffer.0=DisableC_USE_MU_3A_ABUS

DS619 April 7, 2009 www.xilinx.com 9Product SpecificationG46 1=Enable storing MU 6 signals in the data sample storage buffer.0=DisableC_USE_MU_6A_SLV_